Abstract


In past few years, deep learning has been the state-of-the-art technique in many intelligent applications which process increasing larger and complex real-world input data, such as image, video, voice, text, etc. Both embedded and high performance systems turn to ASIC accelerators as cost and performance effective alternative to traditional processing platforms, including CPUs, GPUs, FPGA, DSP. Among all the ASIC designs, DianNao family, a set of high efficient accelerators suitable for systems from embedded to server end, has long been the most influential architecture designs. In this tutorial, we will provide architecture design details of several members of DianNao family: DianNao, the world-first deep learning processor; DaDianNao, a multi-core processor for supercomputers; PuDianNao, a pervasive processor for Machine Learning techniques; ShiDianNao, an extreme efficient accelerator for near-camera intelligent vision processing.

Targeted Audience and Scope


The tutorial session content is planned for a full day event. This tutorial is targeted for people from deep learning related working fields as well as other various fields, especially researchers and graduate students who are interested in architecture design, ASIC implementation, deep learning, neural networks, machine learning, and systems. In this tutorial, we will keep trying to talk in a comprehensive way with content for both beginners and professional audience. Thus, every audience could get exposed in the topic in an easy, smooth and progressive manner.

Schedules


   9:00-9:10    Overall Introduction
   9:10-9:35    DianNao: a small-footprint high-throughput accelerator for ubiquitous machine-learning
  9:35-10:00    DaDianNao: A Machine-Learning Supercomputer
10:00-10:25    PuDianNao A Polyvalent Machine Learning Accelerator
10:25-10:40    Break
10:40-11:05    ShiDianNao: Shifting Vision Processing Closer to the Sensor
11:05-11:30    Cambrion-X: An Accelerator for Sparse Neural Networks
11:30-11:55    Cambricon: An Instruction Set Architecture for Neural Networks